In a typical peak detector circuit, a storage capacitor (SCAP) is charged by an emitter follower driver transistor which acts as a low impedance source of signal. Even with such a source, a finite time is required for the capacitor charge to rise to the peak value of the signal. In the interests of accuracy, the SCAP should be as large as possible. However, as the size of the capacitor is increased, it takes longer for it to reach its peak charge value. Therefore, the peak detector design must be a compromise that attempts to optimize the circuit characteristics in terms of the overall function. It is to be understood that a peak detector produces a DC output which is proportional to the AC peak signal input value. As long as such proportionality is maintained, the DC output need not actually equal the peak signal input. However, if such equality is necessary, there are circuits that can provide it.
The present invention relates to a gated peak detector. Such circuits include means for electronically turning the circuit on and off in response to a gate control signal. Upon receiving the turn-on signal, the circuit output will rise up to a d-c level proportional to the a-c peak input. However, a finite time is required for the output to achieve its peak-related level and this time interval is called the response time. This response time interval can be undesirably long. It would be desirable to include means for electronically controlling the response time in the peak detector circuit.